1. Field of the Invention
The present invention relates to a semiconductor device and to a method of fabricating the same. More particularly, it relates to semiconductor device suitably applicable to a nonvolatile semiconductor memory in which a floating gate and a control gate are formed via a dielectric film.
2. Description of the Related Art
Recently, a nonvolatile memory such as an EEPROM which holds stored data even when disconnected from a power supply has attracted attention as a semiconductor memory. In this nonvolatile memory, a floating gate is formed on a semiconductor substrate via a tunnel insulating film, and a control gate is formed as to oppose this floating gate via a dielectric film.
One example of this nonvolatile semiconductor memory is disclosed in Japanese Patent Laid-Open No. 6-85279. This element is obtained by turning the above nonvolatile semiconductor memory upside down. More specifically, this nonvolatile semiconductor memory is fabricated by sequentially stacking a gate insulating film, a floating gate, and a tunnel insulating film in an insulating film formed on a semiconductor substrate, and forming a semiconductor layer having a source and a drain on top of the resultant structure. Since contacts can be extracted from the upper surface side, this element facilitates arranging word lines and is suited to increase the degree of integration.
The structure, however, of this nonvolatile semiconductor memory is complicated because the memory has a stacked gate structure, and this extremely increases the accuracy requirements when the element is to be formed. In addition, to lower the write voltage, it is necessary to increase the area of the overlap of the control gate and the floating gate. This not only increases the number of fabrication steps and the fabrication cost and lowers the reliability but also interferes with an increase in the degree of integration.
To solve the above problems, Japanese Patent Laid-Open No. 59-155968 or Japanese Patent Publication No. 7-112018 has disclosed an EEPROM which has a small cell area and includes a single-layer polysilicon film. This EEPROM includes a first element active region formed by forming a source and a drain on a semiconductor substrate and a second element active region formed adjacent to the first element active region via an element isolation structure by forming an impurity diffusion layer. A single-layer polysilicon film is patterned to form a floating gate which Is formed by patterning on a channel between the source and the drain via a tunnel insulating film in the first element active region. This floating gate is formed by patterning to oppose the impurity diffusion layer via a gate insulating film in the second active region. The impurity diffusion layer in the second element active region functions as a control gate.
In the above single-layer gate EEPROM, however, it is necessary to apply a high voltage of 20 (V) or more to the control gate, i.e., the impurity diffusion layer when data is erased or written, especially when data is erased. Consequently, it becomes difficult to ensure a large enough breakdown voltage between the control gate and the semiconductor substrate, leading to a serious problem of an operation error.
Furthermore, Japanese Patent Laid-Open No. 7-147340 has disclosed an EEPROM which has a diffusion layer serving as the control gate separated from other semiconductor area to apply a high voltage to the diffusion layer.
However, it is difficult to minimize variations in the threshold value of the EEPROM and stably perform write and read operations.
It is an object of the present invention to provide a reliable semiconductor device which is a single-layer gate semiconductor device by which a low-cost process is possible, has a control gate which can well withstand a high voltage applied when data is erased or written, and can prevent an operation error, and a method of fabricating the same.
A semiconductor device of the present invention is a semiconductor device comprising a semiconductor substrate in which a first and a second element active regions are demarcated by means of element isolation structure, structure having a shield plate electrode formed on the semiconductor substrate via a first insulating film, a first and a second conductive regions formed on a surface region of the semiconductor substrate in the first element active region, a first electrode formed on the semiconductor substrate between the first and the second conductive regions via a second insulating film, a third conductive region formed in the surface region of the semiconductor substrate in the second element active region, and a second electrode formed on the third conductive region via a dielectric film. The first electrode and the second electrode are electrically connected.
Another aspect of the semiconductor device of the present invention is a semiconductor device comprising a semiconductor substrate in which a first and a second element active regions are demarcated by means of element isolation structure, a first and a second conductive regions formed on a surface region of the semiconductor substrate in the first element active region, a first electrode formed on the semiconductor substrate between the first and the second conductive regions via a second insulating film, a third conductive region formed in the surface region of the semiconductor substrate in the second element active region, and a second electrode formed on the third conductive region via a dielectric film. The first electrode and the second electrode are electrically connected and a third electrode is connected to the semiconductor substrate to apply a predetermined electric potential to the semiconductor substrate in the first element active region.
A method of fabricating a semiconductor device of the present invention comprises the first step of defining first, second, third, and fourth element active regions by forming an element isolation structure on a semiconductor substrate having an insulating layer in a predetermined depth and covering a region from side surfaces to a lower surface of at least the first element active region with the insulating layer and the element isolation structure the second step of forming a first diffusion layer by doping an impurity into said first element active region, the third step of forming a diffusion layer region by doping an impurity having a conductivity type opposite to a conductivity type of the semiconductor substrate into a surface region of the semiconductor substrate in the second element active region, the fourth step of forming first, second, third, and fourth insulating films on the semiconductor substrate in the first, second, third, and fourth element active regions, respectively, the fifth step of forming a conductive film via first, second, third, and fourth insulating films on an entire surface of the semiconductor substrate in the first, second, third, and fourth element active regions, respectively, the sixth step of patterning the conductive film to leave a predetermined pattern in at least one of the first and third element active regions and form gate electrodes in the second and fourth element active regions, the seventh step of doping an impurity into the third and fourth element active regions to form a pair of second diffusion layers and a pair of third diffusion layers in surface regions of the semiconductor substrate on two sides of the conductive film in the third and fourth element active regions, the eighth step of doping an impurity having a conductivity type opposite to a conductivity type of the diffusion layer region into the second element active region to form a pair of fourth diffusion layers in surface regions of the semiconductor substrate on two sides of the conductive film in the second element active region, the ninth step of forming a fifth diffusion layer by doping an impurity into the semiconductor substrate near the third element active region, and the tenth step of forming an electrode connected to the fifth diffusion layer to apply a predetermined voltage to the third element active region via said fifth diffusion layer.
Another aspect of the method of fabricating a semiconductor device of the present invention comprises the first step of defining first and second element active regions by forming an element isolation structure on a semiconductor substrate having an insulating layer in a predetermined depth and covering a region from side surfaces to a lower surface of at least the first element active region with the insulating layer and the element isolation structure, the second step of forming a first diffusion layer by doping an impurity into a surface region of the semiconductor substrate in the first element active region, the third step of forming a first insulating film on the semiconductor substrate in the first element active region and a second insulating film on the semiconductor substrate in the second element active region, the fourth step of forming a conductive film on an entire surface including the first and second element active regions and patterning the conductive film to leave a predetermined pattern in at least one of the first and second element active regions, the fifth step of doping an impurity into an entire surface including the second element active region to form a pair of second diffusion layers in surface regions of the semiconductor substrate on two sides of the conductive film in the second element active region, the sixth step of forming a third diffusion layer by doping an impurity into the semiconductor substrate near the second element active region, and the seventh step of forming an electrode connected to the third layer to apply a predetermined voltage to the second element active region via the third diffusion layer.
Still another aspect of the method of fabricating a semiconductor device of the present invention comprises the first step of forming a first trench in a surface of a nearly flat semiconductor region, the second step of forming a first film having a film thickness larger than a depth of the first trench on an entire surface of the semiconductor region to bury the first trench, the third step of forming a second trench in a portion of the first film above the first trench, the second trench being formed to make a bottom surface of the second trench lower than the semiconductor substrate except for the first trench and not to reach the surface of the semiconductor substrate in the first trench, the fourth step of forming a second film having a film thickness larger than a depth of the second trench on an entire surface of the first film to bury the second trench, and the fifth step of polishing at least the first and second films by using the semiconductor substrate as a stopper, thereby planarizing the surface.
Still another aspect of the method of fabricating a semiconductor device of the present invention comprises the first step of forming a first insulating film on a semiconductor substrate, the second step of doping a first impurity to form a first diffusion layer in a predetermined range of a surface region of the semiconductor substrate, the third step of forming a first conductive film on the first insulating film, the fourth step of selectively removing the first conductive film until the first insulating film is exposed, thereby forming a first island conductive film on the first diffusion layer and a shield plate electrode having a first hole and a second hole which surrounds the first island conductive film and is wider than the first diffusion layer, the fifth step of forming a second insulating film on an entire surface to bury the first island conductive film and the shield plate electrode, the sixth step of defining an element active region by removing the second insulating film and the first insulating film present in the first hole until the semiconductor substrate is exposed, the seventh step of sequentially stacking a third insulating film and a second conductive film on the semiconductor substrate in the element active region, the eighth step of selectively removing the second conductive film to form a second island conductive film via the third insulating film on the semiconductor substrate in at least the element active region, the ninth step of doping a second impurity into an entire surface including the element active region to form a pair of second diffusion layers in surface regions of the semiconductor substrate on two sides of the second island conductive film in the element active region, and the tenth step of forming an integrated floating gate electrode by electrically connecting the first and second island conductive films.
Still another aspect of the method of fabricating a semiconductor device of the present invention comprises the first step of forming a first insulating film on a semiconductor substrate, the second step of doping a first impurity to form a first diffusion layer in a predetermined range of a surface region of the semiconductor substrate, the third step of forming a first conductive film on the first insulating film, the fourth step of selectively removing the first conductive film until the first insulating film is exposed, thereby forming a first island conductive film on the first diffusion layer and a shield plate electrode having a first hole and a second hole which surrounds the first island conductive film and is wider than the first diffusion layer, the fifth step of forming a second insulating film on an entire surface to bury the first island conductive film and the shield plate electrode, the sixth step of defining an element active region by removing the second insulating film and the first insulating film present in the first hole until the semiconductor substrate is exposed, the seventh step of forming a third insulating film on the semiconductor substrate in the element active region, the eighth step of forming a hole which exposes the first island conductive film in the second insulating film, the ninth step of filling the hole by forming a second conductive film on an entire surface including the element active region, the tenth step of selectively removing the second conductive film so as to leave a pattern extending from the hole to the element active region, thereby forming a floating gate electrode integrated with the first island conductive film, and the eleventh step of doping a second impurity into the element active region to form a pair of second diffusion layers in surface regions of the semiconductor substrate on two sides of the second conductive film in the element active region.
Still another aspect of the method of fabricating a semiconductor device of the present invention comprises the first step of forming a first insulating film in a predetermined region on a semiconductor substrate and a second insulating film on the semiconductor substrate not covered with the first insulating film, the second step of doping a first impurity to form a first diffusion layer in a surface region of the semiconductor substrate below the second insulating film, the third step of forming a first conductive film on the first and second insulating films, the fourth step of selectively removing the first conductive film until the first or second insulating film is exposed to form a first island conductive film on the first diffusion layer and a second island conductive film on the first insulating film, and simultaneously forming a shield plate electrode having holes surrounding the first and second island conductive films, the fifth step of forming a floating gate electrode by electrically connecting the first and second island conductive films, and the sixth step of doping an impurity into the hole surrounding the second island conductive film to form a pair of second diffusion layers in surface regions of the semiconductor substrate on two sides of the second island conductive film.
In the present invention, a conductor layer which functions as the control gate of a nonvolatile semiconductor memory is formed in a surface region of a semiconductor substrate, and a region from the side surfaces to the lower surface of this conductor layer is completely covered with an insulating film. Therefore, even when a high voltage is applied to the control gate to erase data, a high breakdown voltage can be held in the outer portion of the conductor layer. Also, a pair of diffusion layers is formed in surface regions of the semiconductor substrate on the two sides of a tunnel oxide film of the nonvolatile semiconductor memory, and an electrode is formed to apply a predetermined substrate potential to an element active region including these diffusion layers. Accordingly, it is possible to minimize variations in the threshold value and stably perform write and read operations.
The present invention can realize a reliable semiconductor device which is a single-layer gate semiconductor device by which a low-cost process is possible, has a control gate which can well withstand a high voltage applied when data is erased or written, and can prevent an operation error.